1. Field of the Invention
The invention relates in general to nonvolatile semiconductor memory devices and more particularly to a memory employing flat-type memory cells.
2. Description of the Prior Art
Read only memories, generally referred to as nonvolatile memories, typically have memory cell arrangements which are classified as NOR-typed or NAND-typed cell arrays in accordance with logic circuit definitions. The NOR-typed cell array has the advantage of obtaining efficient current drive capability, but it causes a shortage of space by its cell size. The advantage and disadvantages are reversed in the NAND-typed cell array. Due to the relative strength and weakness of the two cell array types, a flat-type cell array has been proposed as a successful solution for the read only memories. The flat-type cell array is, in digital logic standard, a kind of NOR-typed arrangement.
Nonvolatile memories having the flat-type memory cell array have been disclosed in several articles, e.g., "12-Mb ROM Design Using Bank Select Architecture" (88 SYMPOSIUM ON VLSI CIRCUITS, VI-7, pp.85-86). The architecture of the memory cell array of the preceding article is shown in FIG. 1, wherein memory cell blocks are selected by activating selection signals SOm (for odd columns) and SEm (for even columns) where SOm-1 and SEm+1 conduct for adjacent memory blocks. Bit lines are classified into main bit line MBi-1 to MBi+2 and sub bit lines SB2i-3 to SB2i+4. Every two sub bit lines are subjected to one main bit line, and main bit lines MBi-1 and MBi+1 act as virtual ground lines.
During a read operation, in order to select a memory cell, for example, RC13, power supply voltage Vcc is applied to word line WL1 and ground voltage Vss is applied to other word lines WL2 to WLn. Main bit line MBi-1 is connected to Vss while main bit line MBi is being activated. The discharging current at the forced condition flows starting from main bit line MBi, and then through odd column selection transistor T05, sub bit line SB2i-1, memory cell RC14, even column selection transistor TE5, main bit line MBi-1, column gate transistor TY1, ground selection transistor TG1 and Vss, and in that order. Sense amplifier, connected to MBi through column gate transistor TY2, generates a data bit "1" or "0" from detecting a voltage level on MBi which is determined by a threshold voltage of selected memory cell RC13.
Assuming that when a read operation is conducted for memory cell RCn2 with a threshold voltage VT ranged from 0V to Vcc (0&lt;VT&lt;Vcc; hereinafter, such a memory cell may be called "on-cell"), MBi is pulled down and then sense amplifier SAx reads "0". The discharging current at this time flows, as shown with the broken line in FIG. 1, starting from main bit line MBi, odd column selection transistor T05, sub bit line SB2i-1, memory cell RCn2, odd column selection transistor T03, main bit line MBi-1, column gate transistor TY1, ground selection transistor TG1 and Vss, in that order.
Since sources and drains of the adjacent memory cells are connected to diffusion regions which are formed in a semiconductor bulk (or substrate), a voltage drop, caused by conductive on-cells, is substantially made up throughout the resistance in diffusion regions by which the sub bit line is constructed. Thus, the amount of the current flowing through the on-cell (e.g., RCn2) is delimited by the diffusion resistance involved in the source and drain regions as well as the sub bit lines. A more detailed description of the current where a piece of information is read out from memory cell RCn2 is provided with reference to FIG. 2. In this case, as shown in FIG. 2, the aforementioned current meets resistance r2 of a partial diffusion region which connects odd column selection transistor T05 to memory cell RCn2 and resistance r1 of a partial diffusion region which connects memory cell RCn2 to odd column selection transistor T03.
While, assuming that when another read operation is being conducted for memory cell RC12 with a threshold voltage larger than Vcc (VT&gt;Vcc; hereinafter, such a memory cell may be called as "off-cell"), main bit line MBi must be pulled up to a high level of voltage and thereby sense amplifier SAx must detect "1" from the main bit line MBi. But, if other memory cells RC13 to RC17 connected to word line WL1 which activates the memory cell RC12 are held up in an on-cell, the current from sense amplifier SAx flows into adjacent main bit lines (e.g., MBi+1, MBi+2, . . . ) through the adjacent memory cells connected to W11 and odd column selection transistors responding to odd column selection signal SOm, while there is no current path towards the main bit line MBi-1 due to the nonconductive memory cell RC12. The unwanted current entrance into the adjacent bit lines makes it difficult for the main bit line MBi to retain the high level, so that a read-out time for data bit "1" becomes longer in proportion to the current amount induced thereby.
The current degradation due to the parasitic resistances of the diffusion regions has been considered in U.S. Pat. No. 5,280,442 (hereinafter the '442 patent) which powers the degradation rate of sensing current. FIG. 3 illustrates the architecture of memory cell array disclosed in the '442 patent, using the same dimensions of FIG. 1. In FIG. 3, memory blocks are arranged in the row direction, each memory block being numbered with odd and even numbers therein, and sub bit lines SB2i-3 to SB2i+4 are interposed between the memory blocks. Each sub bit line is connected in common to memory cells of adjacent memory blocks, and main bit lines MBi-1 to MBi+2, arranged in parallel with the sub bit lines, are positioned in columns by groups of two. One main bit line is connected to the three sub bit lines, such that main bit line Mbi-1 is connected to SB2i-3 through odd column selection transistor TOi-1 at node NOi-1, to SB2i-1 through TEi at node NEi-1 and directly to SB2i-2. When memory cell RCn2 of FIG. 3 is selected, the current path is formed, as shown in FIG. 3, through main bit line MBi, odd column selection transistor TOi, sub bit line SB2i-1, memory cell RCn2, main bit line MBi-1 and Vss, and in this order.
FIG. 4 shows a more advanced configuration which provides a better current drivability compared to the configuration shown in FIG. 2, in which the sensing current flows through two transistors and parasitic resistances. However, the circuit architecture as shown in FIG. 3 has at least a bit line capacitance value of at least four times that of the bit line capacitance value in FIG. 1, at a node (e.g., NOi) at which the main bit line and sub bit line are coupled to each other (note that main bit line of FIG. 1 is just connected to source and drain diffusion regions between cell transistors). A main bit line is connected to a sub bit line coupled to source and drain diffusion regions between adjacent cell transistors, and further to such two sub bit lines. Therefore, assuming that memory cell RC12 is selected and is on off-cell, when main bit line MBi goes to a high level and thereafter the data bit is read out as "1" from a sense amplifier corresponding to the main bit line MBi, the increased capacitance engaged in the main bit line causes the read-out time for "1" to be longer than that of the arrangement shown in FIG. 1.
Even in the architecture shown in FIG. 3, as the architecture shown in FIG. 1, unwanted leak current may flow toward a non selected adjacent main bit line through memory cell transistors and odd column selection transistors during a read operation for an on-cell.
With the circuit arrangements of the cell arrays depicted either in FIG. 1 or in FIG. 3, the enhancement the read-out speed for data (particularly for "1") stored in memory cells is still under development for the numerous reasons mentioned heretofore, and the above mentioned problems are also applicable to high density and fast nonvolatile memories.